The present disclosure relates to the field of digital computer systems, and more specifically, to a method for controlling access to a cache memory.
Recent microprocessor architecture allows software to use so-called “virtual” (or sometimes called “logical”) addresses to reference memory locations. The memory access itself is done using a “physical” (or sometimes called “absolute”) address. To translate between the two, typically a data structure called Translation Lookaside Buffer (TLB) is involved. The process of translating is sometimes called Dynamic Address Translation (DAT), in particular in the IBM z/Architecture.
In a typical microprocessor system, several levels of caches are used to speed up memory accesses by keeping a copy of the memory contents “close” to the processor core. With cache implementations supporting DAT, a frequently used implementation indexes into the cache directory using part of the logical address, and the so-called “tag” information that the lookup request is compared against is using absolute addresses. This requires a translation of the logical address as used by the program into an absolute address, usually involving a lookup in the TLB.
However, with ever growing microprocessor core caches, TLBs also have to grow, and the power consumption of the TLB lookup in addition to the directory lookup is a significant contributor to microprocessor core power. Also, the size of the TLB is limited by timing constraints, as the TLB lookup itself will become part of the critical path.
A “virtual cache” stores translation information in the cache directory instead of a TLB. This saves the power and latency involved in the TLB lookup. However, in a non-virtual cache design, the same cache line can be “used” by different translations at the same time. This is possible because these different logical to absolute translations can co-exists in a TLB. In the virtual cache, only the translation information stored in the cache directory can be used.
One important case where multiple different translations to the same absolute address are used in parallel is related to multithreading: Software running on different threads on the same core may share memory, even if the CPU architecture (such as the z/Architecture) defines TLB entries as not shareable between threads. So, multiple threads can use the same address translations, but will have different TLB entries. Shared libraries can complicate the matter, as they often use different translation for different threads.